This invention relates to superconducting integrated circuits and, in particular, to high speed superconducting analog-to-digital converters (ADCs).
Important measures of the performance of an ADC include speed, i.e., the sampling rate in samples converted per second, resolution or sensitivity as measured by the smallest change that can be measured in an analog signal and dynamic range. Ultrafast superconducting digital circuits may be fabricated using Josephson junctions (JJs) integrated together according to RSFQ (rapid-single-flux-quantum) Logic. Furthermore, JJs are well suited to form a natural high-resolution ADC, since a voltage V applied across a JJ (with appropriate damping) generates a rapid sequence of single-flux-quantum (SFQ) digital pulses at a rate determined by fundamental constants defined by f=2 eV/h, where: f is frequency, V is the voltage applied across the JJ, “e” is the charge on an electron, and “h” is Planck's constant. Conversely, a pulse stream applied to a JJ may be used to generate a voltage defined by V=fh/2e.
Using JJs to form ADCs results in an approach which is quite different than that used in conventional semiconductor ADCs. A superconducting ADC may include a Josephson-junction modulator (ADC front-end) followed by an RSFQ digital filter to generate additional digital bits to increase the dynamic range of the ADC. The entire circuit may be constructed using Josephson junction integrated-circuit fabrication technology. This leads to superior performance (effective numbers of bits of dynamic range) with relatively simple circuit architecture.
The present state of the art and problems associated therewith may be illustrated with reference to the simplified prior art analog-to-digital converter (ADC) circuit shown in FIGS. 1 and 1A. An analog input signal is applied to a single junction quantizer 31 to which is also applied an SFQ pulse stream of frequency fc/2. This SFQ pulse stream applied to the quantizer functions to generate (either directly or indirectly) a steady state bias voltage value (corresponding to fc/2). Where the quantizer is designed to operate at a maximum frequency of fc, and the quantizer is to be operated symmetrically about the steady state bias, the value of the bias voltage (VB) is dictated by system considerations to be equal to a voltage corresponding to fc/2. The analog input to the single junction quantizer is the sum (combination) of the bias and the analog input and is designed to vary between zero and two times the bias voltage (i.e., the dynamic range extends in terms of voltage between zero and 2VB and in term of frequency between zero and fc). That is, in response to the analog voltage at its input (which can be proportional either to the ADC input signal or to its time derivative), the single junction quantizer 31 produces a frequency modulated output whose maximum rate is equal to fc. The phase modulated output of the quantizer 31 is fed to a phase demodulator 33 (and a digital decimation filter 35) which needs to be operated at a frequency equal to fc to enable synchronous operation for proper processing of the ADC signals.
As is evident from FIG. 1A, the single junction quantizer circuit provides a single output pulse train whose rate (frequency) is a direct function of the analog input voltage applied to the JJ of the quantizer; that is, f=2 eV/h, as noted above. For this circuit configuration, the components of the quantizer circuit, and in particular the JJ, JJQ, must switch at the (highest) rate (fc) corresponding to the highest value of analog input voltage to be converted by the quantizer circuit. This imposes significant constraints on the maximum speed of response at which the circuit can provide a linear response.
In the circuit of FIG. 1A, the system is designed such that the maximum rate of the pulses at the output of the quantizer is fc. This is done to ensure proper processing of the output pulses generated by the ADC when they are applied to what is referred to as the synchronizing circuitry (31, 35) which is operated at a rate of fc. To have the output of the quantizer 31 operate at a maximum rate of fc when the analog input signal is at its specified maximum level, the quantizer has to be biased at fc/2, or at a corresponding voltage VB, which causes the output of the quantizer to be fc/2, when the analog input signal is zero (neither positive nor negative). The dynamic range is thus limited by the requirement that the bias level be a voltage level which corresponds to fc/2 (with the maximum specified input signal being a voltage corresponding to fc). There thus exits a limitation on the dynamic range of the input signal which can be processed linearly by the single junction quantizer.
The problems discussed above pertaining to switching speed and dynamic range are overcome in circuits embodying the invention.